In the design of static random access memories (SRAMs), one of the important problems that has limited the performance of the SRAM is the need to provide a proper timing sequence when a READ operation follows a WRITE operation. This has been called the "READ-after-WRITE" problem. A READ operation which follows a WRITE operation must be adequately delayed until the bit lines are precharged to their proper high level so that they subsequently can be discharged during the READ operation, as required. If the READ operation follows too quickly on the heels of a WRITE operation, the bitlines will not reach their correct precharge level. The necessity of guaranteeing that the READ does not occur prematurely often detracts from the overall performance of prior art SRAMs.